Circuit Design and Optimization

ABSTRACT

A method implemented on a data processing system for circuit design is described. The method comprises identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via nets, and determining whether timing of an element of a particular first portion is sensitive to degradation of a signal from a net associated with the particular first portion. In one embodiment, the method further comprises reporting the determination.

The present invention is a continuation of U.S. patent application Ser.No. 13/668,113, filed on Nov. 2, 2012, which is a divisional of U.S.patent application Ser. No. 12/363,212, which is now U.S. Pat. No.8,307,315, issued on Nov. 6, 2012.

TECHNOLOGY FIELD

The invention relates to circuit design, and more particularly to theanalysis and synthesis of a design of a circuit.

BACKGROUND

For the design of digital circuits (e.g., on the scale of Very LargeScale Integration (VLSI) technology), designers often employcomputer-aided techniques. Standard languages such as HardwareDescription Languages (HDLs) have been developed to describe digitalcircuits to aid in the design and simulation of complex digitalcircuits. Several hardware description languages, such as VHDL andVerilog, have evolved as industry standards. VHDL and Verilog aregeneral-purpose hardware description languages that allow definition ofa hardware model at the gate level, the register transfer level (RTL) orthe behavioral level using abstract data types. As device technologycontinues to advance, various product design tools have been developedto adapt HDLs for use with newer devices and design styles.

In designing an integrated circuit with an HDL code, the code is firstwritten and then compiled by an HDL compiler. The HDL source codedescribes at some level the circuit elements, and the compiler producesan RTL netlist from this compilation. The RTL netlist is typically atechnology independent netlist in that it is independent of thetechnology/architecture of a specific vendor's integrated circuit, suchas field programmable gate arrays (FPGA) or an application-specificintegrated circuit (ASIC). The RTL netlist corresponds to a schematicrepresentation of circuit elements (as opposed to a behavioralrepresentation). A mapping operation is then performed to convert fromthe technology independent RTL netlist to a technology specific netlist,which can be used to create circuits in the vendor'stechnology/architecture. It is well known that FPGA vendors utilizedifferent technology/architecture to implement logic circuits withintheir integrated circuits. Thus, the technology independent RTL netlistis mapped to create a netlist, which is specific to a particularvendor's technology/architecture.

One operation, which is often desirable in this process, is to plan thelayout of a particular integrated circuit and to control timing problemsand to manage interconnections between regions of an integrated circuit.This is sometimes referred to as “floor planning.” A typical floorplanning operation divides the circuit area of an integrated circuitinto regions, sometimes called “blocks,” and then assigns logic toreside in a block. These regions may be rectangular or non-rectangular.This operation has two effects: the estimation error for the location ofthe logic is reduced from the size of the integrated circuit to the sizeof the block (which tends to reduce errors in timing estimates), and theplacement and routing typically runs faster because as it has beenreduced from one very large problem into a series of simpler problems.

After placement of components on the chip and routing of wires betweencomponents, timing analysis (e.g., transient timing simulation, orstatic timing analysis) can be performed to accurately determine thesignal delays between logic elements. Back annotation can be performedto update a more-abstract design with information from later designstages. For example, back annotation reads wire delay information andplacement information from the placement and route database to annotatethe logic synthesis design. Back annotated delay information can be usedto identify critical paths where the timing requirements are notsatisfied; and logic synthesis may be improved to meet the timingrequirements.

After the design layout (e.g., the placement and routing), only limitedoptimizations like resizing or buffering (known as in placeoptimizations) are typically performed. However, in place optimizationscan provide only limited improvements. When the in place optimizationcannot adjust the solution to meet the timing constraint, adjustment tothe logic synthesis may be performed, leading to the expensive iterationbetween logic synthesis and placement and routing.

Timing analysis results can be expressed in terms of slack, which is thedifference between the desired delay and the actual (estimated orcomputed) delay. When the desired delay is larger than the actual delay,the slack is positive; otherwise, the slack is negative. Typically, itis necessary to make the slack positive (or close to zero) to meet thetiming requirement (e.g., through reducing the wire delay to increasethe slack). For example, during synthesis, a total negative slackalgorithm (e.g., used in a circuit design compiler, Synplify, availablefrom Synplicity, Inc., California) considers all instances whose slackis negative as candidates for improvement, since any one of thecandidates with negative slack could become critical after physicaldesign. It is typical to make the slack positive to ensure that thetiming requirements are met.

After the synthesis transformation, the placement and routing isperformed to generate a technology/architecture dependent design layout,which can be implemented on a vendor's technology/architecture dependentintegrated circuit, such as field programmable gate arrays (FPGA) or anapplication-specific integrated circuit (ASIC).

SUMMARY OF THE DESCRIPTION

Methods and apparatuses for a design of a circuit are discussed. In oneaspect of an embodiment, a method for designing a circuit includesidentifying one or more first portions of a design of a circuit, each ofthe one or more first portions containing a set of elementsinterconnected via timing nets and generating weights for the timingcritical nets, the weights being generated after identifying the one ormore first portions and executing a placer algorithm which uses theweights for the timing critical nets to place the set of elements on arepresentation of the design. In this method, in one embodiment, theweights for the timing critical nets can be generated to have valuesthat differ from weights for non-critical nets. The placer algorithm canbe any one of a variety of conventional placer algorithms such as aweighted wire length driven placer algorithm or a force directed timingdriven placer algorithm or a min-cut placer algorithm.

The placer algorithm can provide a full placement solution for allelements of the design and in certain embodiments can provide a refinedplacement solution for less than all of the elements of the design. Inone implementation of this embodiment, the identifying of the timingislands and the generating of the weights for the timing critical netsin those timing islands and the executing of the placer algorithm may beperformed iteratively until a placement solution is decided to convergeto a desired result. In one implementation, the method can furtherinclude generating at least one additional net(s) that does notrepresent an electrical connection, the at least one additional netbeing within only a timing island, and the placer algorithm uses the atleast one additional net (which may be referred to as a pseudonet) as ahint to provide a placement solution.

The present invention includes methods and apparatuses which performthese methods, including data processing systems which perform thesemethods, and computer readable media which when executed on dataprocessing systems cause the systems to perform these methods. Otherfeatures of the present invention will be apparent from the accompanyingdrawings and from the detailed description which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings in which likereferences indicate similar elements.

FIG. 1 illustrates a method to extract a timing critical portion of adesign of a circuit according to one embodiment of the presentinvention.

FIG. 2 illustrates a way to visualize the timing structure of a circuitaccording to one embodiment of the present invention.

FIG. 3 illustrates a way to display timing analysis results according toone embodiment of the present invention.

FIG. 4 illustrates cross probing based on timing structures of a circuitaccording to one embodiment of the present invention.

FIG. 5 illustrates floor planning based on timing structures of acircuit according to one embodiment of the present invention.

FIG. 6 illustrates a method to report module dependency based on timingstructures of a circuit according to one embodiment of the presentinvention.

FIG. 7 illustrates a method to report circuit dependency based on timingstructures of a circuit according to one embodiment of the presentinvention.

FIGS. 8-11 illustrate synthesis transformations to isolate timingdependency for the timing structures of a circuit according toembodiments of the present invention.

FIGS. 12-14 illustrate methods of utilizing identified timing structuresof a circuit for circuit design and optimization according toembodiments of the present invention.

FIGS. 15A, 15B, and 15C show examples of methods that use timing islandinformation in the process of performing placement according to at leastcertain embodiments.

FIG. 16A shows an example of a method for creating pseudonets which areused in a placer algorithm according to at least certain embodiments.FIG. 16B shows an example of a pseudonet.

FIG. 17 shows an example of how timing island information can be usedwith a force driver placer algorithm.

FIG. 18A shows an example of a cluster which has at least one externalnet.

FIGS. 18B and 18C show examples of methods that use timing islandinformation in the process of partitioning of clusters or placingclusters.

FIG. 19 shows a block diagram example of a data processing system whichmay be used with the present invention.

DETAILED DESCRIPTION

The following description and drawings are illustrative of the inventionand are not to be construed as limiting the invention. Numerous specificdetails are described to provide a thorough understanding of the presentinvention. However, in certain instances, well known or conventionaldetails are not described in order to avoid obscuring the description ofthe present invention. References to one or an embodiment in the presentdisclosure are not necessarily references to the same embodiment; and,such references mean at least one.

When analyzing the critical timing in a design, it is rare to find acase where there is a single critical path. A critical path can beconsidered to be a path or net which does not satisfy a timingrequirement. A path includes two end points connected by a number ofcircuit connections (nets) and circuit elements. An end point istypically a sequential element (e.g., a register, a flip-flop, a memoryelement, etc.) or a port or pin of a module.

Commonly there is a section of the design where there are a number ofcritical paths that share common intermediate combinatorial instances.Thus, these critical paths are directly interconnected with each otherto form a timing critical section (or timing critical net) of thedesign. Such collection of timing critical instances that shareconnectivity with a critical path may be called an island. Given adesign that fails to meet timing requirements, it is common for thedesign to contain multiple islands.

FIG. 1 illustrates a method to extract a timing critical portion of adesign of a circuit according to one embodiment of the presentinvention.

A timing analysis typically can provide the timing analysis result (105)that includes the list of timing critical paths of the design (101) of acircuit.

For example, according to the timing analysis result (105), a portion(103) of the circuit design includes a number of timing critical paths.The path (S1-E1-E2-S2) from sequential element S1 (111) to element E1(113), element E2 (115) and sequential element S2 (117) is a criticalpath. Further, the path (S1-E1-E3-S4) from sequential element S1 (111)to element E1 (113), element E3 (135) and sequential element S4 (137) isalso a critical path. Thus, critical paths (S1-E1-E2-S2) and(S1-E1-E3-S4) share elements and interconnect directly with each other.Therefore, critical paths (S1-E1-E2-S2) and (S1-E1-E3-S4) can beconsidered as on a same island which is a timing critical portion of thedesign.

Further, the path (S3-E4-E3-S4) from sequential element S3 (131) toelement E4 (133), element E3 (135) and sequential element S4 (137) isalso a critical path. Thus, the critical path (S3-E4-E3-S4) is also onthe same island.

The path (S2-E7-S7) from sequential element S2 (117) to element E7(121), and sequential element S7 (123) is also a critical path. Sincepaths (S1-E1-E2-S2) and (S2-E7-S7) share the same sequential element S2,they can be considered as on the same island. Alternatively, since paths(S1-E1-E2-S2) and (S2-E7-S7) pass cross the sequential element S2, theymay be considered as on different islands. Thus, according to a designor implementation preference, the islands may or may not expand acrossend points.

The path (S5-E5-E6-S6) from sequential element S5 (141) to element E5(143), element E6 (145) and sequential element S6 (147) is also acritical path. Timing critical path (S5-E5-E6-S6) is on an island.However, since the path (S1-E5-E6-S6) is not a critical path, path(S5-E5-E6-S6) is not directly connected to the island of paths(S1-E1-E2-S2), (S1-E1-E3-S4), and (S3-E4-E3-S4). Thus, path(S5-E5-E6-S6) is on a different island.

In one embodiment of the present invention, the extraction of an islandstarts from a critical path. Any other critical path that shares one ormore intermediate element, or the same starting point, or the sameending point are selected as being on the same island with the criticalpath. The expansion of the island can be optionally allowed to passacross end points. For example, if two paths that share the sequentialelement but one as the starting point and the other as the ending point,these two paths may optionally be considered as on the same island.

In one embodiment of the present invention, the elements of the firstcritical path are added to the island. If another critical path has asame element as the island, the elements of this critical path are alsoadded into the island; and this critical path is marked as on theisland. Thus, the island can be expanded in this fashion until it isdetermined that critical paths are either on the island or not on theisland. A critical paths not on the island can then be selected as theseed for the next island, which can be expanded in the similar fashion.Through such a process, the critical paths can be grouped into islands.

Alternatively, islands can be extracted through examining the netsconnected to the already identified elements of the elements. During theexpansion of an already identified portion of an island, if a netdriving an element of the island is critical (on a critical path), thedriver element of the net is also on the island. Similarly, if a netthat is being driven by an element of the island is critical (on acritical path), the critical load elements of the net are also on theisland. The expansion may or may not cross end points (e.g., sequentialelements). Thus, each island represent a single critical-net-connectedgraph of elements. In a connected graph, any two has a connected path inbetween.

Islands may be graphically visualized when the circuit design isrepresented on a three-dimensional graph where instances are assigned a“height” or altitude attribute according to the negative slack.

FIG. 2 illustrates a way to visualize the timing structure of a circuitaccording to one embodiment of the present invention.

In FIG. 2, instances interconnected by the nets have a “height”according to their negative slack. A threshold (S_(threshold)) is usedto define a desired critical level. A critical slack is less thanS_(threshold); and a non-critical slack is more than S_(threshold).Thus, the threshold (S_(threshold)) defines the “water” level fordefining the islands (201, 203, 205, 207). The elements in an island(e.g., 201) have critical nets that interconnect the elements of theisland. No critical net interconnects the elements of two differentislands. Under the “water” level, the non-critical elements andnon-critical nets connect the islands together to form the connectedcircuit.

From FIG. 2, one can see the timing critical portions of the circuit andthe timing structure of the circuit. Such timing structures of circuitare typically different from function-based module hierarchy.

Critical paths often span across function-based module hierarchy. Floorplanning logical blocks often degrades performance. From FIG. 2, it isseen that the island extraction is connectivity and timing-based. Theislands represent the physical hierarchy where instances of a collectionare physically interconnected. The summit of an island is a mostcritical path of the collection. Lower altitudes of island contain nearcritical paths.

The display of islands can provide guidance to RTL design planning. Forexample, the islands indicate which RTL objects should be floor plannedtogether. Different islands can be floor planned into separate regions.When a design contains very large islands, the RTL design may bere-coded to break up the islands.

A hierarchical island-based timing report can be used to provide easyunderstanding of critical paths. The hierarchical island-based timingreport contains a hierarchical display for groups of connected criticalpaths, islands, enabling faster timing closure. In one embodiment, afterthe timing analysis and island extraction, the results are saved to thehierarchical based island timing report file. The timing results areorganized in the hierarchy of islands, critical paths, and elementinstances. The timing report is useful when creating physicalconstraints by identifying which instances belong to multiple criticalpaths and how the critical paths in an island group are connectedtogether.

In one embodiment, an island timing report is a substantially textualreport that lists the islands and their slack values.

In one embodiment of the present invention, the island timing report canbe used to select start and end points for a single island, cross-probeto the other views, such as a gate view, HDL view, RTL view (such as theRTL view shown in FIG. 1), technology view, physical view, etc. An HDLview shows the HDL design of the circuit. An RTL view shows the RTLschematic of the circuit design. A technology view shows the synthesizedschematic of the technology-mapped circuit design. A physical view showsthe physical layout of the placement design.

For example, the island-based cross-probe can be used to show a filteredRTL view that contains all the start and end points for the island. Thepaths can be further expanded to show a filtered RTL view that containsall the instances in the island. These instances can be selected andassigned to a block region.

In one embodiment, post placement and routing timing information can beback annotated into the database to provide an island timing report thathas the accurate timing information.

In one embodiment, the island timing report provides information aboutgroups of critical instances that cannot easily be obtained intraditional path-only based timing reports. Using the island timingreport, an engineer can quickly and easily identify the instances thatwill benefit from being constrained to a block region. Cross-probingfrom the island timing report to an HDL analysis view or solution makesit fast and easy to apply physical constraints to the islands identifiedin the report.

FIG. 3 illustrates a way to display timing analysis results according toone embodiment of the present invention.

In FIG. 3, a hierarchical island-based timing report (305) providesicons representing individual islands (e.g., 315) and icons representingindividual paths (e.g., 317) in the islands. For each of the criticalpaths in an island, the worst slack and the longest path delay arepresented. The display of islands can be expanded to show the pathswithin the islands (e.g., by selecting the icon 311 to show the paths in“island 2”). The display of islands can also be collapsed to hide thepaths within the corresponding islands (e.g., by selecting the icon 313to hide the paths in “island 1”).

When an island is selected, selecting the button “Detail (303) allowsthe user to see the further detailed timing information about theisland.

When an island is selected, selecting the button “Cross Probe” (301)allows the user to see the island in other views, such as in an HDLview, an RTL view (e.g., technology dependent or technologyindependent), a physical view, etc.

FIG. 4 illustrates cross probing based on timing structures of a circuitaccording to one embodiment of the present invention.

In FIG. 4, when the user selects island “I1” in the text view (401)using the cursor (407), the element instances in the schematic view(403), or physical view (405), of the island is highlighted, accordingto user-selected options. In FIG. 4, all element instances of thecross-probed island are highlighted. Alternatively, the user may selectto highlight only the end points.

FIG. 5 illustrates floor planning based on timing structures of acircuit according to one embodiment of the present invention.

In FIG. 5, the user can select an island from the text view (503) andassign the island to a block of a floor planning view (501) (e.g., block511 or 513). In one embodiment, the circuit is only partially floorplanned, which allows the design tool to have more room to optimize thelayout for the remaining portion of the circuit. Floor planning theislands without floor planning the remaining portion of the circuit canlead to fast and better solutions.

Traditionally, the floor planning is based on the logical functionblocks. Since the hierarchy of the logical function blocks may notreflect the timing structure of the circuit, the traditional floorplanning approach require a high level of expertise to achieve timingclosure (meet the timing requirements).

When the information about the islands is available, the floor planningbased on the islands becomes much easier.

FIG. 6 illustrates a method to report module dependency based on timingstructures of a circuit according to one embodiment of the presentinvention.

In FIG. 6, the modules (601, 603, 605) represent the traditionallogic-based function blocks. To understand the timing dependency betweenthe modules, the timing critical paths between the modules can beidentified and displayed.

In one embodiment of the present invention, the timing critical pathsbetween the modules are grouped as islands (e.g., 607, 609 and 611).Thus, the timing dependency between the modules can be presented in ahierarchical island-based report.

In one embodiment, the timing critical paths that interconnect themodules are identified. The islands are extracted from the timingcritical paths.

Alternatively, the islands may be extracted from the timing criticalpaths of the entire design. The timing critical paths within the islandsthat interconnect the modules can then be identified and presented inassociation with the islands.

FIG. 7 illustrates a method to report circuit dependency based on timingstructures of a circuit according to one embodiment of the presentinvention.

In FIG. 7, islands (701, 703 and 705) represent different portions oftiming critical circuits. Non-critical logic (e.g., 711, 713, 715, 717)generally interconnects the islands. When the placement of the islandsis changed, portions of the non-critical logic may become critical.Thus, it is helpful to understand the criticality of the non-criticallogic that connects to the islands.

Further, two islands with many connections may be floor planned close toeach other.

In one embodiment of the present invention, affinity scores are used topresent the relationships between the islands. In one embodiment, anaffinity score between two islands increases as the number of pathsbetween the islands increases and as the slacks of these paths decrease.Thus, two islands with a high affinity score are to be floor plannedclose to each other than to other islands.

In one embodiment of the present invention, synthesis transformationsare performed to isolate timing criticality within the islands. Once theislands are isolated, the islands can be more easily floor planned; andtiming closure can be achieved faster.

FIGS. 8-11 illustrate synthesis transformations to isolate timingdependency for the timing structures of a circuit according toembodiments of the present invention.

In FIG. 8, an island (801) includes elements (811, 813, 815, 817, . . .). Element (813) drives the net (818) which is not critical. However,increasing the wire length for the net (818) may increase the capacitiveload of the element (813), which may slow down the element (813). Toisolate the effect of the capacitive coupling on the speed of theelement (813), a synthesis transformation (803) can be performed toinsert a buffer (819) to isolate the timing dependency within the island(805). The inserted buffer (819) is considered as a part of the islandso that the element instances within the island are floor planned in thesame block.

FIG. 9 illustrates an alternative synthesis transformation (833) toisolate the timing island (801). In FIG. 9, the driver (813) isreplicated. The replicated instant (831) drives the non-critical net(837) and thus isolates the timing dependency within the island (835).

In FIG. 10, an island (851) includes elements (811, 813, 815, 817, . . .). Element (815) is driven by the net (809) which is non-critical.However, increasing the wire length for the net (809) may degrade thesignal driven by the element (807), which can slow down the element(815). To isolate the change in wire length of the net (809) on thespeed of the element (815), a synthesis transformation (853) can beperformed to insert a buffer (857) to isolate the timing dependencywithin the island (855). The inserted buffer (855) is considered as apart of the island so that the element instances within the island arefloor planned in the same block.

FIG. 11 illustrates an alternative synthesis transformation (873) toisolate the timing island (851). In FIG. 11, the driver (807) isreplicated. The replicated instant (879) drives the element (815)through a short net and thus isolates the timing dependency within theisland (875). The replicated driver 879 is considered part of the island875.

FIGS. 12-14 illustrate methods of utilizing identified timing structuresof a circuit for circuit design and optimization according toembodiments of the present invention.

In FIG. 12, after operation 901 determines one or more islands in adesign of a circuit (e.g., from importing the definitions from a file oranalyzing the list of critical paths of the design), operation 903reports inter-dependency between portions of the circuit in view ofislands (e.g., affinity of the islands, critical inter-module pathsgrouped according to islands, etc.).

In FIG. 13, after operation 911 identifies an island in a design of acircuit (e.g., from importing the definitions from a file or analyzingthe list of critical paths of the design), operation 913 performs asynthesis transformation of the island to isolate timing dependency ofthe island on a non-critical net connected to an element of the island.

In FIG. 14, operation 921 performs a timing analysis of a design of acircuit to determine timing critical paths. Operation 923 extractsislands of the design according to the timing analysis (and a slackthreshold which defines the “water” level).

Optionally, operation 925 cross probes the islands of the design ondifferent design views of the circuit (e.g., HDL view, RTL view,physical layout view, text view).

For example, one can view the elements of an island highlighted in thephysical layout view. If the elements of the island scatter in thephysical layout view, it is an indication that the timing of the islandcan be significantly improved if the island is floor planned in a block.

For example, one can inspect the HDL view to decide whether or not tochange the design to break up large islands.

Optionally, operation 927 displays inter-module critical paths asgrouped according to the hierarchy of islands, paths and elements. Thehierarchical presentation of islands, paths and elements for criticalpaths that interconnect modules helps a designer to visualize the timingproblems.

Optionally, operation 929 computes and presents affinity scores for theislands. When the floor planning the islands, the affinity of theislands helps a designer to determine the relative positions of theislands with respect to each other.

Operation 931 determines timing sensitivity of islands to non-criticalnets connected to the islands. Operation 933 performs synthesistransformations (e.g., inserting buffers, replicating drive elements,etc) to isolate timing sensitivity of islands from the non-critical netsconnected to the islands. Once the islands are not sensitive to thenon-critical nets, different islands can be more freely floor plannedinto different blocks. Operation 935 selects the islands for floorplanning (e.g., in view of island affinity, etc.).

Certain aspects of the invention relate to the use of timing islandinformation in various parts of the circuit design process or flow (e.g.design of VLSI ASICs or FPGAs). For example, the timing islandinformation can be used during the process or flow of placing circuitcomponents in the circuit design process or flow.

A placement process during VLSI design (ASIC/FPGA) determines thephysical locations of circuit components on the semiconductor chip. Thecomponents cannot be overlapping with each other. One of the objectivesof the placement process is to minimize the sum of length of the nets(connections) which connect the circuit components. The nets representthe electrical connections between the circuit components. The timingdelay through a net is proportional to the length of the net (the exactrelation between net length and delay is complex and can be differentfor different semiconductor technologies like FPGAs/ASICs). Net lengthsare affected by the physical locations of the driving component and theload components of the net. Hence actual physical locations of thecircuit components affect the timing characteristics of the circuit.Timing-driven placement seeks to minimize the delay of the longest validtiming path in the circuit (or maximize the worst slack of the design).In the industry/academia VLSI placement process is performed by varioustypes of algorithms such as min-cut partitioning, simulated annealing,force directed, analytical etc. In one embodiment of the invention, thetiming island information can be used during the process of automatictiming driven placement to generate better placements of the circuitcomponents that maximizes the slack of the worst timing path in thedesign.

The following references describe various placement algorithms which canbe used with the timing island information in the embodiments describedherein. Quadratic placement techniques are described in “Fast And RobustQuadratic Placement Combined With An Exact Linear Net Model,” PeterSpindler, Frank M. Johannes, November 2006, ICCAD '06: Proceedings ofthe 2006 IEEE/ACM International Conference on Computer-aided Design.Analytical placement techniques are described in “Architecture andDetails of a High Quality, Large-Scale Analytical Placer,” A. B. Kahng,S. Reda and Q. Wang, Proc. ACM/IEEE Intl. Conference on Computer-AidedDesign, November 2005; and in “Multilevel Generalized Force-DirectedMethod for Circuit Placement,” Tony F. Chan, Jason Cong, and Kenton Sz,Proceedings of the International Symposium on Physical Design, pp.185-192, April 2005. A min-cut placement technique is described in“Unification of Partitioning, Floorplanning and Placement,” S. N. Adya,S. Chaturvedi, J. A. Roy, D. A. Papa and I. L. Markov, Intl. Conferenceon Computer-Aided Design (ICCAD 2004), pp. 550-557. A min-cutpartitioning and VLSI clustering technique is described in “MultilevelHypergraph Partitioning: Applications in VLSI Design,” G. Karypis, R.Aggarwal, V. Kumar, and S. Shekhar, Proc. ACM/IEEE Design AutomationConf., 1997, pp. 526-529. A forcer directed placer algorithm isdescribed in two U.S. patent applications which are incorporated byreference: U.S. application Ser. No. 12/177,867 filed on Jul. 22, 2008,titled “Architectural Physical Synthesis” (attorney docket no.02986.P1116) and U.S. application Ser. No. 12/177,869 filed on Jul. 22,2008, titled “Architectural Physical Synthesis” (attorney docket no.02986.P1117).

Based on a certain slack threshold, timing island information can begenerated to capture the timing structures and timing dependency of thecircuit. Objects in the same timing islands have a certain affinity witheach other since they are connected (either directly or transitively) bynets and are also the critical part of the circuit. Since the lengths ofnets effect the timing of the circuit, it would be advantageous to tryand keep the lengths of nets connecting components on the same timingisland, small in order to minimize the delay of the timing paths throughthe timing island which is critical.

Depending on the specific placement algorithms used during the automaticVLSI placement procedure, several strategies may be employed to achievethe objective of keeping the nets connecting components on the sametiming island, small. These are described herein and are also shown inFIGS. 15A, 15B, 15C, 16A, 16B, and 17.

Before the placement procedure starts one could identify timing islandsbased on estimated lengths/delays of the nets (wireload models). This isshown in operation 1005 if FIG. 15A, which operation follows operations1001 and 1003 in the circuit design flow or method of FIG. 15A. Sincethe timing information is based on estimated net lengths, it is not veryaccurate. Once the timing island information is generated the nets thatconnect the components on the same timing islands can be assigned higherweights (such as operation 1007 in FIG. 15A). A black box placer thatminimizes the weighted wirelength (sum of all nets in the circuit) canthen be used (in operation 1009) to place the appropriately weightedcircuit netlist on the semiconductor fabric. The placer algorithm usedin operation 1009 can be one of a variety of placer algorithms, such asa weighted wire length driven placer algorithm. The placer should ensurethat the higher weighted nets connecting components within the sametiming islands are kept short and hence the island is placed in a tightcluster. Multi-pin nets that have loads in different timing islands orhaving only some loads in a timing island may need to be treateddifferently since the entire net should not be weighted. This aspect isshown in FIGS. 16A and 16B. In the method of FIG. 16A, operation 1065identifies timing islands (e.g. in the manner described herein) andproduces information to identify such timing islands. Then, in operation1067, the method identifies multi-pin nets, such as multi-pin nets 1113,1119, and 1117 shown in FIG. 16B, which connect loads in differenttiming islands or which connect loads in a timing island and other loadswhich are not in the timing island. It can be seen that element 1103 inthe timing island 1101 is connected by a multi-pin net (e.g. same outputdrives multiple inputs to other elements) to elements 1105, 1109 and1111 respectively by nets 1113, 1119 and 1117. In this case a pseudonet1120 is created; this pseudonet 1120 is effectively a duplicate netbetween elements 1103 and 1105. In this case one could introduce one ormore, in operation 1069, new appropriately weighted additional nets(referred to as pseudonets) that connects only the components of theoriginal net which are in the same timing island. The new additionalnets (pseudonets) do not represent an electrical connection, but areonly used as hints for the placer in operation 1071.

The above technique, while general, may not be very accurate since theinitial timing island information is generated based on timing based onestimated net lengths/delays. However the actual net lengths aredetermined during the placement procedure. The timing characteristics ofthe circuit change continuously during the placement procedure as theplacement of the circuit components is being refined. One embodimentcould update the timing island information as a part of the placementprocedure. FIGS. 15B and 15C show two examples of such an embodiment. Asthe placement is being refined, the timing island information could bere-generated. In one embodiment (e.g. operation 1023), the placementalgorithm performs/computes a full placement solution, while in anotherembodiment, the placement algorithm, after an initial placement inoperation 1039, performs a partial or refined placement of only somecomponents (while others are not re-placed). Based on the new timingisland information, the weights of the nets connecting components in thesame timing islands could be re-computed. In this approach the placementprocedure is repeatedly self tuning the timing island information tomake sure that existing and new timing islands remain in a tight clusterand the length of the nets connecting components on the same timingislands is small until a placer solution converges to satisfy theconventional criteria for a satisfactory placement (e.g. congestion,timing, and overlap; or wire length, timing and overlap, etc.). Asdescribed above, the technique of using additional nets (pseudonets) formulti-pin nets that span multiple timing islands or are not a full partof the timing island can be used in this technique also. This techniqueof using the timing islands can be used within any placement procedurethat works in iterations. These include min-cut partitioning basedplacement, force-directed placement, analytical placement and simulatedannealing based placement.

One embodiment of using the timing island information during forcedirected timing driven placement is illustrated in FIG. 17. Forcedirected placement is one of the algorithms used in theindustry/academia to generate placement of circuit components. Theprocedure starts with producing a wirelength (sum of all nets in thecircuit) minimum solution of the circuit components. The nets can bemodeled as attractive forces such as charged particles which attract(such as a positive and a negative particle) and repulsive forces (twoparticles of the same charge) or springs, etc. FIG. 17 shows that eachelement (elements 1143, 1137, 1139, 1141, and 1145) is positivelycharged, tending to repel each other in a placement solution. Positivecharges 1143A, 1137A and 1139A represent the positive charge of theirrespective elements 1143, 1137 and 1139. In addition, each net (such asnets 1149 and 1151) has a positive charge on the output side/end of thenet and a negative charge on the input side/end of the net; this helpsto reduce wire length of a net as each net will, due to this attractiveforce, want to shrink. This physical system can be solved using wellknown mathematical optimization techniques like quadraticprogramming/non-linear programming. However, this placement solution canhave circuit components overlapping with each other which is an illegalplacement. The placement procedure then works in iterations to reduceand eventually remove the overlap between the modules. One way toaccomplish this spreading of the circuit components is to introduceadditional repulsive forces between the circuit components. The systemof attractive net forces and repulsive inter component forces can besolved using existing mathematical techniques like quadraticprogramming/non-linear programming. The spreading (repulsive) forces areadded gradually during iterations to the system to spread the componentsin an orderly fashion to ensure convergence and avoid oscillations. Thetiming island information can be used/incorporated in the forcerplacement process as the placement is being refined (spread). One couldaccomplish this by reducing the relative strength of the repulsiveforces between components belonging to the same timing island ascompared to the normal strengths of repulsive forces between othercomponents. This is shown in FIG. 17; the amount of charge 1137A and1139A (which are in the elements 1137 and 1139 that are part of timingisland 1135) can be reduced relative to the positive charge 1143A (andthe positive charge of element 1145). The timing island 1135 includeselements 1137, 1139 and 1141 and excludes elements 1143 and 1151. Thiswould ensure that the connected components on the same timing islandsspread slower than the other parts of the circuit. At the end of theforce-directed placement procedure the components on the same timingislands should be placed, in one embodiment, in a tight cluster withsmaller relative span, thus reducing the length of nets connecting thecomponents on the same timing islands.

Clustering/packing is used during the VLSI design flow to group severalrelated components in a circuit into a super component or a cluster.Examples of clustering and/or packing are described in the followingreferences: “Multilevel Hypergraph Partitioning: Applications in VLSIDesign,” G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, Proc.ACM/IEEE Design Automation Conf., 1997, pp. 526-529; and “Architectureand CAD for Deep-Submicron FPGAs,” V. Betz et al., Springer Series 1999,describes FPGA packing. Clustering can be used in several contextsduring the VLSI design flow, such as during coarsening phase ofmulti-level partitioning/placement or during legal packing generationfor LAB (Logic Array Block) level FPGA placement, etc. One of thetraditional objectives of clustering is to minimize the external nets ofthe clustered circuit. An external net of a clustered circuit netlist isa net that is incident on multiple clusters. The net 1215 in FIG. 18A isan example of an external net because it is not entirely containedwithin the cluster 1201 which includes elements 1203, 1205, 1207, and1209; the cluster 1201 excludes elements 1211 and 1213. The net 1215 isincident on an element outside of the cluster 1201 and is therefore anexternal net. An internal net, on the other hand, is incident only onthe elements inside a single cluster. Clustering is sometimes usedduring multi-level placement or LAB level FPGA style placement. When aclustered netlist is placed, all the elements in a cluster areconstrained to be placed next to each other. By placing a clusterednetlist as a group, the number of placeable objects in the circuitnetlist is greatly reduced. FIG. 18C shows an example of a method forusing information which identifies timing islands (in operation 1235) inorder to create clusters from and/or based on those timing islands andthen place each cluster as a group (in operation 1237).

Clustering can also be used during a multi-level min-cut partitioningprocedure. Given a top level circuit netlist, one of the traditionalobjectives of a min-cut partitioning procedure has been to minimize cutnets between two or more child partitions subject to area constraints ineach child partition. Clustering can be used to coarsen the initial flatnetlist and reduce the number of instances being partitioned so thatmore efficient partitioning algorithms can be applied on a smallerclustered netlist. FIG. 18B shows an example of a method for usinginformation which identifies timing islands in order to create clustersand then perform partitioning using the clusters created from the timingisland information. In addition to reducing the number of external netsand pin connections, timing driven clustering is also of importance tomaximize the slack of the circuit by reducing the lengths of criticalnets. One can use the timing island information described herein tofigure out the affinity of the various components in the circuit. Oncethe timing island information is generated, during the clusteringprocedure, there can be a higher cost (weights) for cutting(externalizing) nets that connect components in the same timing islands.Thus the clustering procedure would have more incentive to internalizenets that connect components in the same timing islands. Thisessentially means that components on the same timing island would bemore likely to stay in the same clusters than other components.Depending upon the application of clustering, one embodiment could alsomake it a hard constraint to keep all components in the same timingisland in the same cluster subject to the area constraints on eachcluster.

Many of the methods of the present invention may be performed with adigital processing system, such as a conventional, general-purposecomputer system. Special purpose computers, which are designed orprogrammed to perform only one function, may also be used.

FIG. 19 shows one example of a typical computer system which may be usedwith the present invention. Note that while FIG. 19 illustrates variouscomponents of a computer system, it is not intended to represent anyparticular architecture or manner of interconnecting the components assuch details are not germane to the present invention. It will also beappreciated that network computers and other data processing systemswhich have fewer components or perhaps more components may also be usedwith the present invention. The computer system of FIG. 19 may, forexample, be a Sun workstation, or a personal computer (PC) running aWindows operating system, or an Apple Macintosh computer or a Linuxsystem.

As shown in FIG. 19, the computer system 951, which is a form of a dataprocessing system, includes a bus 952 which is coupled to amicroprocessor 953 and a ROM 957 and volatile RAM 955 and a non-volatilememory 956. The microprocessor 953 is coupled to cache memory 954 asshown in the example of FIG. 19. The bus 952 interconnects these variouscomponents together and also interconnects these components 953, 957,955, and 956 to a display controller and display device 958 and toperipheral devices such as input/output (I/O) devices which may be mice,keyboards, modems, network interfaces, printers, scanners, video camerasand other devices which are well known in the art. Typically, theinput/output devices 960 are coupled to the system through input/outputcontrollers 959. The volatile RAM 955 is typically implemented asdynamic RAM (DRAM) which requires power continually in order to refreshor maintain the data in the memory. The non-volatile memory 956 istypically a magnetic hard drive or a magnetic optical drive or anoptical drive or a DVD RAM or other type of memory systems whichmaintain data even after power is removed from the system. Typically,the non-volatile memory will also be a random access memory althoughthis is not required. While FIG. 19 shows that the non-volatile memoryis a local device coupled directly to the rest of the components in thedata processing system, it will be appreciated that the presentinvention may utilize a non-volatile memory which is remote from thesystem, such as a network storage device which is coupled to the dataprocessing system through a network interface such as a modem orEthernet interface. The bus 952 may include one or more buses connectedto each other through various bridges, controllers and/or adapters as iswell known in the art. In one embodiment the I/o controller 959 includesa USB (Universal Serial Bus) adapter for controlling USB peripherals,and/or an IEEE-1394 bus adapter for controlling IEEE-1394 peripherals.

It will be apparent from this description that aspects of the presentinvention may be embodied, at least in part, in software. That is, thetechniques may be carried out in a computer system or other dataprocessing system in response to its processor, such as amicroprocessor, executing sequences of instructions contained in amemory, such as ROM 957, volatile RAM 955, non-volatile memory 956,cache 954 or a remote storage device. In various embodiments, hardwiredcircuitry may be used in combination with software instructions toimplement the present invention. Thus, the techniques are not limited toany specific combination of hardware circuitry and software nor to anyparticular source for the instructions executed by the data processingsystem. In addition, throughout this description, various functions andoperations are described as being performed by or caused by softwarecode to simplify description. However, those skilled in the art willrecognize what is meant by such expressions is that the functions resultfrom execution of the code by a processor, such as the microprocessor953.

A machine readable medium can be used to store software and data whichwhen executed by a data processing system causes the system to performvarious methods of the present invention. This executable software anddata may be stored in various places including for example ROM 957,volatile RAM 955, non-volatile memory 956 and/or cache 954 as shown inFIG. 19. Portions of this software and/or data may be stored in any oneof these storage devices.

Thus, a machine readable medium includes any mechanism that provides(i.e., stores and/or transmits) information in a form accessible by amachine (e.g., a computer, network device, personal digital assistant,manufacturing tool, any device with a set of one or more processors,etc.). For example, a machine readable medium includesrecordable/non-recordable media (e.g., read only memory (ROM); randomaccess memory (RAM); magnetic disk storage media; optical storage media;flash memory devices; etc.).

In the foregoing specification, the invention has been described withreference to specific exemplary embodiments thereof. It will be evidentthat various modifications may be made thereto without departing fromthe broader spirit and scope of the invention as set forth in thefollowing claims. The specification and drawings are, accordingly, to beregarded in an illustrative sense rather than a restrictive sense.

What is claimed is:
 1. A method implemented on a data processing systemfor circuit design, the method comprising: identifying one or more firstportions of a design of a circuit, each of the one or more firstportions containing a set of elements interconnected via nets;determining whether timing of an element of a particular first portionis sensitive to degradation of a signal from a net associated with theparticular first portion; reporting the determination.
 2. The method ofclaim 1, further comprising: in response to a determination ofsensitivity to degradation, the reporting including a recommendation toisolate the element.
 3. The method of claim 1, further comprising:receiving user input to select one of the first portions to assign in ablock in a floor plan; and floor planning the corresponding one of thefirst portions in the block according to the user input.
 4. The methodof claim 1, further comprising: receiving input to select one of thefirst portions to re-assign in a block in a floor plan; and floorplanning the corresponding one of the first portions in the blockaccording to the input.
 5. The method of claim 1, further comprising:identifying a plurality of functional modules of the design of thecircuit; and identifying critical paths interconnecting the plurality offunctional modules, wherein reporting the determination includespresenting the critical paths grouped according to the first portions.6. The method of claim 5, wherein one or more of the nets in theplurality of the first portions comprises critical paths interconnectingthe functional modules.
 7. The method of claim 1, wherein the timing ofthe element is visualized in a cross-probe to other views of the circuitdesign.
 8. A method implemented on a data processing system for circuitdesign, the method comprising: identifying a first portion of a designof a circuit, the first portion containing a set of elementsinterconnected via nets; and isolating a timing dependency of the firstportion on a net connected to an element of the first portion.
 9. Themethod of claim 8, wherein the timing dependency is visualized in across-probe to other views of the circuit design.
 10. The method ofclaim 9, wherein the cross-probe is visualized as an RTL view of thecircuit design.
 11. The method of claim 9, wherein the cross-probe isvisualized as an HDL view of the circuit design.
 12. The method of claim9, wherein the cross-probe is visualized as a three-dimensional graph ofthe circuit design.
 13. The method of claim 8, wherein each of the firstportions is a single critical-net connected graph of elements.
 14. Themethod of claim 9, wherein the cross-probe visualized in a second viewshows elements of critical paths in the corresponding one of the firstportions.
 15. The method of claim 8, wherein each of the first portionsis a single critical-net connected graph of elements.
 16. A methodimplemented on a data processing system for circuit design, the methodcomprising: identifying a first portion of a design of a circuit, thefirst portion containing a set of elements interconnected via nets; andisolating a timing dependency of the first portion on a net connected toan element of the first portion.
 17. The method of claim 16, wherein theisolating comprises: inserting a buffer on the net as part of the firstportion.
 18. The method of claim 16, wherein the isolating comprises:replicating a drive element of the non-critical net as part of the firstportion.
 19. The method of claim 16, wherein the net is a net driving anelement of the first portion and the isolating is performedautomatically in response to identifying the first portion.
 20. Themethod of claim 19, further comprising: determining whether timing ofthe element of the first portion is sensitive to capacitive load;wherein the isolating is performed when the element is sensitive tocapacitive load.